NV-APROC main goal is to significantly decrease the power consumption of processors , by one order of magnitude of the total power consumption, compared to conventional volatile systems, by proposing a novel hybrid clock-less non-volatile architecture. The targeted circuit will use the so-called asynchronous design technique , which is already well known to be energy efficient, and MRAM emerging non-volatile technology (peSTT and SOT) which has a really interesting set of features in terms of write / read energy and CMOS process integration and compatibility. In order to demonstrate the potential of such an approach, which is expected to be huge, we propose to benchmark our innovative work up to full layout with state of the art synchronous version of the processor.
WP1 will be fully dedicated to project coordination. Strategic coordination, administrative & financial management, exploitation, dissemination of results through conferences, journals will be managed. WP1 will be the responsibility of the coordinator.More information
WP2 aims at providing magnetic tunnel junction simulation model for full custom design, including both non-volatile logic and memories. CAD tool environment will be developed.More information
WP3 is dedicated to the low power processor and non-volatile memory specifications and design.More information
WP4 deals with high level of integrated circuit design. Specific high level simulation framework environment will be developed as well as metrics.More information