WP 3 - Processor and memory design, implementation and simulation

Muller cell
Muller cell


WP3 is dedicated to the low power processor and non-volatile memory specifications and design.


  • Innovative peSTT-MRAM and SOT-MRAM IP design.
  • Non-volatile low-power processor design.
  • Characterization of non-volatile IPs: performance and power consumption.
SOT-MRAM memory
SOT-MRAM memory

Description of work

FlexNode: an FPGA prototype for sensor node.

Top-level specifications

These specifications will be used as a guideline for all the other developments, from technology to design, and will first address the top-level entity, with the different components and their interfaces. We will define a set of benchmark applications and a set of metrics (performance, energy, reliability) in order to compare the different designs. We will provide the set of parameters, including size (data width, number of words) and type of the memories, memories interfaces, bus protocol interface, and processor interface.

Design and characterization of a low power processor

It consists in designing a low power processor using non-volatile cells. After RTL validation, logic synthesis and physical implementation up to full layout, timing performance and power consumption will be characterized using back annotated simulations to provide a set of results on various operating points in order to allow system-level analysis. In this part, benchmarking for any feature comparison will be addressed.